(1) Field of the Invention
The present invention generally relates to a method and apparatus for detecting a pseudo noise pattern for a remote loopback test, and more particularly to a method and apparatus for detecting a pseudo noise pattern used for a remote loopback test in which a data circuit-terminating equipment connected to one end of a data transmission line activates another circuit-terminating equipment coupled to the other end thereof.
(2) Description of the Prior Art
A data terminal equipment for use in data communication is coupled to a data transmission line via a data circuit-terminating equipment. When two data terminal equipments located on both sides of the transmission line communicate with each other, data is transferred between the data circuit-terminating equipments provided for the respective data terminal equipments.
In order to test and maintain such data circuit-terminating equipments, a remote loopback test has been recommended by the CCITT Recommendation V.54, the disclosure of which is hereby incorporated by reference. In the recommended remote loopback test, one of the two data circuit-terminating equipments opposite to each other via a data transmission line (normally including an exchange) instructs the other data circuit-terminating equipment to start the remote loopback test. In the above remote loopback test, it is desired that a particular pattern (pseudo noise pattern) be efficiently detected by each of the activated data circuit-terminating equipments located on both sides of the data transmission line.
FIG. 1A shows a data communication system in which the recommended remote loopback test is used, FIG. 1B shows a data circuit-terminating equipment, and FIG. 1C shows how the recommended remote loopback test is activated and carried out. The data communication system shown in FIG. 1A is composed of data terminal equipments (DTE-A and DTE-B) 1, two data circuit-terminating equipments (DCE-A and DCE-B) 2, and a data transmission line 3 composed of a transmit line and a receive line. The data circuit-terminating equipments DTE-A and DTE-B are located on both sides of the data communication line 3, and are coupled with each other. The data circuit-terminating equipments DTE-A and DTE-B simultaneously send and receive data in the two directions at a bit rate equal to, for example, 64K bps (bit per second). Data transmitted via the data transmission line 3 is, for example, an AMI (Alternate Mark Inversion) code, which is a bipolar code. By using the AMI code, it is possible to transmit data at a higher speed than that obtained with a modem (modulator/demodulator) used.
In the past time, the data circuit-terminating equipment 2 was formed of a specific hardware configuration or an (Large Scale Integrated circuit). However, recently, the data circuit-terminating equipment 2 has been configured, as shown in FIG. 1B. The data circuit-terminating equipment 2 shown in FIG. 1B is composed of a data circuit-terminating block 2-1, a microprocessor 2-2, and a data terminal interface block 2-3 connected to terminal 50. It is possible to meet various requirements for the data circuit-terminating equipment 2 by changing firmware formed in the microprocessor 2-2. The functions in common to the various requirements are implemented by hardware or LSIs which form the data circuit-terminating block 2-1 and the data terminal interface block 2-3.
The remote loopback test is carried out in such a case where new data terminal equipment and data circuit-terminating equipment are installed or a fault such as data error occurs. Referring to FIG. 1C, when the data terminal equipment DTE-A receives an instruction to execute the remote loopback test, the data circuit-terminating equipment DCE-A sends a signal showing the activation of the remote loopback test to the data circuit-terminating equipment DCE-B via the data transmission line.
The procedure on the remote loopback test is recommended by the CCITT Recommendation V.54. The recommended procedure will be described below. At the first step of the remote loopback test procedure, the data circuit-terminating equipment DCE-A sends 16 127-bit PN (Pseudo Noise) patterns to the data transmission line. The 127-bit PN pattern (also referred to as a 2.sup.7 PN pattern) is obtained by scrambling binary zeros (0) by a generating polynomial 1+X.sup.-4 +X.sup.-7 (X is a variable), and has 127 bits within one period. The 16 127-bit patterns (16 periods) function as a loopback activating signal. The bit rate at which the PN pattern is sent is set to a normal bit rate of the data circuit-terminating equipment DCE-A. The criterion for detecting the PN pattern by the other data circuit-terminating equipment DCE-B is not specified.
At the second step of the remote loopback test procedure, when the data circuit-terminating equipment DCE-B detects the PN pattern, it sends to the data transmission line 16 127-bit PN patterns (2048 bits), each being generated by scrambling binary ones (1) by the generating polynomial 1+X.sup.-4 +X.sup.-7. The bit rate at which the PN pattern is sent is set to a normal bit rate of the data circuit-terminating equipment DCE-B. The criterion for detecting the PN pattern by the other data circuit-terminating equipment DCE-A is not specified. The 16 127-bit PN patterns function as a confirmation signal. After sending the confirmation signal to the data transmission line, the data circuit-terminating equipment DCE-B forms a loopback path. The data circuit-terminating equipment DCE-A detects the confirmation signal, and enters into a test state (mode) after a time amounting to 2048 bits has elapsed.
At the third step of the remote loopback test procedure, the data circuit-terminating equipment DCE-A sends to the data transmission line 64 127-bit PN patterns (64 periods), each being obtained by scrambling binary ones by the generating polynomial 1+X.sup.-4 +X.sup.-7. Subsequently, the data circuit-terminating equipment DCE-A sends 64 consecutive binary ones to the data transmission line. The 64 127-bit PN patterns and 64 consecutive binary ones form a completion signal.
It can be seen from the above description that it is necessary to provide each of the data circuit-terminating equipments DCE-A and DCE-B with a means for detecting the 127-bit PN pattern. Conventionally, the detection of the loopback activating signal, the confirmation signal or the completion signal uses firmware which has a program in which a ROM table having all 127-bit PN patterns generated by the generating polynomial 1+X.sup.-4 +X.sup.-7 is formed. Each 127-bit PN pattern is compared with the PN patterns in the ROM table. Theoretically, there are no identical 7-bit patterns in the 127-bit PN pattern. Thus, it is possible to detect the PN pattern by comparing seven consecutive bits received with seven consecutive bits at a position in the 127 bits in the ROM table.
However, data is received in serial form without having frame information (provided for use in synchronization), and thus there is a possibility that the seven received bits are not the same as the seven bits read out from the ROM table.
Taking into account such a possibility, a procedure shown FIG. 2 is carried out when the PN pattern detection is started. The seven consecutive bits received are compared with six different patterns, in which there is a one-bit phase difference between the adjacent patterns. Each time seven consecutive bits are received, the comparing procedure shown in FIG. 2 is carried out in accordance with flowcharts shown in FIGS. 3A and 3B. The flowcharts shown in FIGS. 3A and 3B, which are executed by the microprocessor 2-2 shown in FIG. 1B, are a procedure executed at the beginning of the PN pattern detection and an in-detection procedure executed after the procedure shown in FIG. 3A, respectively.
At step 70 where the data circuit-terminating equipment 2 is in a loopback activating signal hunting state, the microprocessor 2-2 receives seven consecutive bits via the data line terminating block 2-1. At subsequent step 71, the microprocessor 2-2 compares the seven consecutive bits received with six patterns as shown in FIG. 2. When it is determined, at step 71, that the seven consecutive pattern is the same as one of the six patterns, the microprocessor 2-2 switches to an in-detection state at step 72. On the other hand, when the seven consecutive bits are not the same as any of the six patterns, the data circuit-terminating equipment 2 returns to the hunting state 70 at step 73.
During the in-detection state at step 74 subsequent to step 72, the microprocessor 2-2 increments the address of the ROM table by +1, so that an updated address of the ROM table indicating the next seven-bit pattern at step 75. At step 76, the microprocessor 2-2 compares the next seven consecutive bits received with the seven-bit pattern indicated by the updated address. When it is determined, at step 76, that the both the 7-bit patterns are the same as each other, the value in a register which stores the number of times that the pattern coincidence is detected is incremented by +1 at step 77. When the value in the register becomes equal to a predetermined value (which corresponds to the number of bits defined by the CCITT Recommendation V.54), the detection procedure ends. On the other hand, when it is determined, at step 76, that both the seven-bit patterns are not the same as each other, the microprocessor 2-2 returns to the hunting state 70 at step 78. At the same time, the above-mentioned register is reset.
However, the above-mentioned prior art has the following disadvantages. First, it is necessary to use two different firmware structures which respectively correspond to the procedures shown in FIGS. 3A and 3B. This needs a large amount of complex software. Second, during the procedure shown in FIG. 3A, the microprocessor 2-2 on the receive side waits for the received seven bits which are the same as the seven bits at a certain position of the 127-bit pattern. Thus, in the worst case, the seven bits are hunted and the PN pattern detection procedure shown in FIG. 3B starts after the data circuit-terminating equipment on the transmitter side has sent 127 consecutive bits (one period). Thus, it takes a long time to start the detection procedure shown in FIG. 3B.